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Samsung SGH-V200 service manual

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SERVICE Manual


1. GSM General SpecificationG S M900Pha se 1EG S M 900P hase 2D CS 1800P has e 1P CS1900F r eq. Band[ MH z ]U plink/D ow nlink890~ 915935~ 960880~915925~9601710~17851805~18801850~ 19101930~ 1990A RF CN r ange 1~ 1240~ 124 &975~1023512~885 512~ 810T x/Rx s pacing 45MH z 45MH z 95M H z 80MH zMod. B it r ate/Bi t Pe riod270. 833kbps3. 692us270. 833kbps3. 692us270.833kbps3.692us270. 833kbps3. 692usT im e S lotP er iod/F r ame Pe r iod576. 9us4. 615ms576. 9us4. 615m s576.9us4.615m s576. 9us4. 615msModula tion 0. 3G MS K 0.3G MS K 0. 3GM SK 0. 3G MS KMS P ow er 33dB m~ 13dBm 33dBm ~5dBm 30dBm ~0dB m 30dBm~ 0dBmPow e r C las s 5pcl ~ 15pcl 5pcl ~ 19pcl 0pcl ~ 15pcl 0pcl ~ 15pclS ensi tivity -102dB m - 102dBm - 100dBm - 100dBmTD M A Mux 8 8 8 8Cell Ra dius 35K m 35Km 2K m -SAMSUNG Proprietary-Contents may change without notice


2. GSM TX power classTX Powercontrol levelGSM900TX Powercontrol levelDCS1800TX Powercontrol levelPCS19005 332 dBm0 303 dBm0 303 dBm6 312 dBm1 283 dBm1 283 dBm7 292 dBm2 263 dBm2 263 dBm8 272 dBm3 243 dBm3 243 dBm9 252 dBm4 223 dBm4 223 dBm10 232 dBm5 203 dBm5 203 dBm11 212 dBm6 183 dBm6 183 dBm12 192 dBm7 163 dBm7 163 dBm13 172 dBm8 143 dBm8 143 dBm14 152 dBm9 124 dBm9 124 dBm15 132 dBm10 104 dBm10 104 dBm16 113 dBm11 84dBm11 84dBm17 93dBm12 64 dBm12 64 dBm18 73 dBm13 44 dBm13 44 dBm19 53 dBm14 25 dBm14 25 dBm15 05 dBm15 05 dBmSAMSUNG Proprietary-Contents may change without notice


0 1) RX PART1. ASM(U1005) Switching Tx, Rx path for GSM900, DCS1800 and PCS1900 by logic controlling.2. ASM Control Logic (U701, U702, U703) Truth TableVC1 VC2 VC3GSM Tx Mode H L LDCS / PCS Tx Mode L H LPCS Rx Mode L L HGSM / DCS Rx Mode L L L3. FILTERTo convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.- GSM FILTER (C1003,C1004,L1001) For filtering the frequency band between 925 ~ 960 MHz- DCS FILTER (C1005,C1006,L1002) For filtering the frequency band 1805 and 1880 MHz.- PCS SAW FILTER (F1003) For filtering the frequency band between 1930 and 1990 MHz4. TC-VCXO (OSC801)To generate the 13MHz reference clock to drive the logic and RF.After additional process, the reference clock applies to the U900 Rx IQ demodulator and Tx IQ modulator.The oscillator for RX IQ demodulator and Tx modulator are controlled by serial data to select channel and use fast lockmode for GPRS high class operation.5. Si 4200 (U901)This chip integrates three differential-input LNAs.The GSM input supports the E-GSM, DCS input supports the DCS1800, PCS input supports the PCS1900. The LNAinputs are matched to the 200 ohm differential output SAW filters through eternal LC matching network.Image-reject mixer downconverts the RF signal to a 100 KHz intermediate frequency(IF) with the RFLO from SI4133Tfrequency synthesizer. The RFLO frequency is between 1737.8 ~ 1989.9 MHz.The Mixer output is amplified with an analog programmable gain amplifier(PGA), which is controlled by AGAIN.The quadrature IF signal is digitized with high resolution A/D converts (ADC).6. Si 4201 (U900)The SI4201 down-converts the ADC output to baseband with a digital 100 KHz quadrature LO signal. Digital decimationand IIR filters perform channel selection to remove blocking and reference interface signals.After channel selection, the digital output is scaled with a digital PGA, which is controlled with the DGAIN. DACs drivea differential analog signal onto the RXIP, RXIN, RXQP, RXQN pins to interface to standard analog-input baseband IC.SAMSUNG Proprietary-Contents may change without notice


2) TX PARTBaseband IQ signal fed into offset PLL, this function is included inside of U902 chip.SI4200 chip generates modulator signal which power level is about 1.5dBm and fed into Power Amplifier(U1008).The PA output power and power ramping are well controlled by AutoPower Control circuit. We use offset PLL below200kHz offset30 kHz bandwidthGSMDCSPCS-35dBc-35dBc-35dBcModulation Spectrum400kHz offset30 kHz bandwidthGSMDCSPCS-66dBc-65dBc-66dBc600kHz ~ 1.8MHz offset30 kHz bandwidthGSMDCSPCS-75dBc-68dBc-75dBc2. Baseband Circuit description of <strong>SGH</strong>-<strong>V200</strong>1. PSC20061.1. Power ManagementSeven low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimalsystem performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0V, and 5.0VSIMs, while a self-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions,such as an LED driver and two call-alert drivers, aid in reducing both board area and system complexity.A three-wire serial interface unit(SIU) provides access to control and configuration registers. This interface gives amicroprocessor full control of the PSC2006 and enables system designers to maximize both standby and talk times.Supervisory functions. including a reset generator, an input voltage monitor, and a thermal monitor, support reliable systemdesign. These functions work together to ensure proper system behavior during start-up or in the event of a faultcondition(low microprocessor voltage, insufficient battery energy, or excessive die temperature).1.2. Battery Charge ManagementA battery charge management block provides fast, efficient charging of a single-cell Li-ion battery. Used in conjunctionwith a current-limited voltage source and an external PMOS pass transistor, this block safely conditions near-dead cellsand provides the option of having fast-charge and top-off controlled internally or by the system's microprocessor.1.3. Backlight LED DriverThe backlight LED driver is a low-side, programmable current source designed to control the brightness of the keyboardand LCD illumination. The driver is enabled by EN_LED, and its current setting is determined by LED[0:2]. ProvidedEN_LED is 1, the driver can be programmed to sink from 12.5mA to 100mA in 12.5mA steps. LED_DRV iscapable of sinking 100mA at a worst-case maximum output voltage of 0.6V. For efficient use, the LEDs is connectedbetween the battery and the LED_DRV output.SAMSUNG Proprietary-Contents may change without notice


1.4. Vibrator Motor DirverThe vibrator motor driver is a low-side, programmable voltage source designed to drive a small dc motor that silentlyalerts the user of an incoming call. The driver is enabled by EN_VIB, and its voltage setting is determined by VIB[0:2].Provided EN_VIB is a logic 1, the driver can be programmed to maintain a motor voltage of 1.1V to 2.5V in 20mVsteps and while sinking up to 100mA. For efficient use, the vibrator motor should be connected between the main batteryand the VIB_DRV output.2. Connector2-1. LCD ConnectorLCD is consisted of main LCD(color 65K STN LCD) and small LCD(4-gray LCD). Chip select signals of EMI part inthe trident, CLCD_EN_FO and GLCD_EN_FO, can enable Each LCD. LED_EN_FO signal enables white LED of mainLCD and EL_EN_FO signal enables EL of small LCD. These two signals are from IO part of the DSP in the trident.RST signal from 2006 initiates the initial process of the LCD.16-bit data lines(D(0)_FO~D(15)_FO) transfers data and commands to LCD through emi_filter. Data and commands useA(2)_FO signal. If this signal is high, Inputs to LCD are commands. If it is low, Inputs to LCD are data. The signalwhich informs the input or output state to LCD, is required. But this system is not necessary this signal. SoCP_WEN_FO signal is used to write data or commands to LCD. Power signals for LCD are V_bat and V_ccd.SPK1P and SPK1N from CSP1093 are used for audio speaker. And VIB_EN_FO from enables the motor.2-2. JTAG ConnectorTrident has two JTAG ports which are for ARM core and DSP core(DSP16000). So this system has two port connectorfor these ports. Pinsinitials for ARM core are CP_and pinsinitials for DSP core are DSP_. CP_TDI andDSP_TDI signal are used for input of data. CP_TDO and DSP_TDO signals are used for the output of the data. CP_TCKand DSP_TCK signals are used for clock because JTAG communication is a synchronous. CP_TMS and DSP_TMSsignals are test mode signals. The difference between these is the RESET_INT signal which is for ARM core RESET.2-3. IRDAThis system uses IRDA module, HSDL_3201, HPs. This has signals, IRDA_EN(enable signal), IRDA_RX(input data)and IRDA_TX(output data). These signals are connected to PPI of trident. It uses two power signals. V_ccd is used forcircuit and V_bat is used for LED.2-4. Keypad connectorThis is consisted of key interface pins among PPI in the trident, KEY_ROW[0~4] and KEY_COL[0~4]. These signalscompose the matrix. Result of matrix informs the key status to key interface in the trident. Some pins are connected tovaristor for ESD protection. And power on/off key is seperated from the matrix. So power on/off signal is connected withPSC2006 to enable PSC2006. SVC_GREEN, SVC_RED and SVC_BLUE are from OCTL of CSP1093. These signalsdecide the color of LED, <strong>service</strong> indicator. Eighteen key LED use the V_bat supply voltage. These are connected toBACKLIGHT signal in the PSC2006. This signal enables LEDs with current control. FLIP_SNS informs the status offolder (open or closed) to the trident. This uses the hall effect IC, A3210ELH. A magnet under main LCD enablesA3210ELH which is on the key FPCB.SAMSUNG Proprietary-Contents may change without notice


2-5. EMI FilterThis system uses the EMI filter, KNA32200-W3 to protect noise from LCD part. Some control signals are connected toLCD without EMI filter.3. IF connetorIt is 24-pin connector, and uses 18-pin at present. They are designed to use SDS, DEBUG, DLC-DETECT, JIG_ON,VEXT, VTEST, VF, CF, VBAT and GND. They connected to power supply IC, microprocessor and signal processor IC.4. AudioAOUTAP from CSP1093 is connected to the main speaker. AOUTAN is connected to the speaker via audio-amp.AOUTBN and AOUTBP are connected to the ear-mic speaker via ear-jack. MICIN and MICOUT are connected to themain MIC. And AUXIN and AUXOUT are connected to the Ear-mic.YMU762MA3 is a LSI for portable telephone that is capable of playing high quality music by utilizing FM synthesizerand ADPCM decorder that are included in this device.As a synthesis, YMU762MA3 is equipped 16 voices with differenttones. Since the device is capable of simultaneouslygenerating up to synchronous with the play of the FM synthesizer, various sampled voices can be used as sound effects.Since the play data of YMU762MA3 are interpreted at anytime through FIFO, the length of the data(playing period) isnot limited, so the device can flexiblysupport application such as incoming call melody music distribution <strong>service</strong>. Thehardware sequencer built in this device allows playing of the complex music without giving excessive load to the CPU ofthe portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time soundgeneration, allowing, for example, utilization of various sound effects when using the game software installed in theportable telephone.YMU759 includes a speaker amplifier with high ripple removal rate whose maximum output is 550mW (SPVDD=3.6V).The device is also equipped with conventional function including a vibartor and a circuit for controlling LEDssynchornous with music.For the headphone, it is provided with a stereophonic output terminal.For the purpose of enabling YMU762MA3 to demonstarte its full capablities, Yamaha purpose to use "SMAF:Syntheticmusic Mobile Application Format" as a data distribution format that is compatible wiht multimedia. Since the SMAF takesa structure that sets importance on the synchronization between sound and images, various contents can be written into itincluding incoming call melody with words that can be used for traning karaoke, and commercial channel that combinestexts, images and sounds, and others. The hardware sequencer of YMU762MA3 directly interprets and plays blocksrelevant to systhesis (playing music and reproducing ADPCM with FM synthesizer) that are included in data distributed inSMAF.5. MemoryThis system uses SHARPs memory, LRS1395. It is consisted of 128M bits flash memory and16M bits SRAM. It has16 bit data line, D[0~15] which is connected to trident, LCD or CSP1093. It has 22 bit address lines, A[1~22]. They areconnected too. CP_CSROMEN and CO_CSROM2EN signals, chip select signals in the trident enable two memories. Theyuse 3 volt supply voltage, V_ccd and 1.8 volt supply voltage, Vcc_1.8a in the PSC2006. During wrting process, CP_WENis low and it enables writing process to flash memory and SRAM. During reading process, CP_OEN is low and it outputinformation which is located at the address from the trident in the flash memory or SRAM to data lines. Each chip selectsignals in the trident select memory among 2 flash memory and 2 SRAM. Reading or writing procedure is processed afterCP_WEN or CP_OEN is enabled. Memories use FLASH_RESET, which is buffered signal of RESET from PSC2006, forESD protection. A[0] signal enables lower byte of SRAM and UPPER_BYTE signal enables higher byte of SRAM.SAMSUNG Proprietary-Contents may change without notice


6. TridentTrident is consisted of ARM core and DSP core. It has 20K*16bits RAM 144K*16bits ROM in the DSP. It has4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted of timer, one bit input/output unit(BIO), JTAG,EMI and HDS(Hardware Development System). ARM core is consisted of EMI, PIC(Programmable Interrupt Controller),reset/power/clock unit, DMA controller, TIC(Test Interface Controller), peripheral bridge, PPI, SSI(Synchronous SerialInterface), ACC(Asynchronous communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface.DSP_AB[0~8], address lines of DSP core and DSP_DB[0~15], data lines of DSP core are connected to CSP1093.A[0~20], address lines of ARM core and D[0~15], data lines of ARM core are connected to memory, LCD and YMU759.ICP(Interprocessor Communication Port) controls the communication between ARM core and DSP core.CSROMEN, CSRAMEN and CS1N to CS4N in the ARM core are connected to each memory. WEN and OEN controlthe process of memory. External IRQ(Interrupt ReQuest) signals from each units, such as, YMU, Ear-jack, Ear-mic andCSP1093, need the compatible process.Some PPI pins has many special functions. CP_KB[0~9] receive the status from key FPCB and are used for thecommunicatios using IRDA(IRDA_RX/TX/EN) and data link cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR). AndUP_CS/SCLK/SDI, control signals for PSC2006 are outputted through PPI pins. It has signal port for charging(CHG_DET,CHG_STAT0), SIM_RESET and FLIP_SNS with which we knows open.closed status of folder. It has JTAG controlpins(TDI/TDO/TCK) for ARM core and DSP core. It recieves 13MHz clock in CKI pin from external TCXO and receives32.768KHz clock from X1RTC. ADC(Analog to Digital Convertor) part receives the status of temperature, battery typeand battery voltage. And control signals(DSP_INT, DSP_IO and DSP_RWN) for DSP core are used. It enables main LCDand small LCD with DSP IP pins.7. CSP1093CSP1093 integrates the timing and control functions for GSM 2+ mobile application with the ADC and DAC functions.The CSP1093 interfaces to the trident, via a 16-bit parallel interface. It serves as the interface that connects a DSP to theRF circuitry in a GSM 2+ mobile telephone. DSP can load 148 bits of burst data into CSP1093s internal register, andprogram CSP1093s event timing and control register with the exact time to send the burst. When the timing portion ofthe event timing and control register matches the internal quarter-bit counter and internal frame counter, the 148 bits inthe internal register are GMSK modulated according to GSM 2+ standards. The resulting phase information is translatedinto I and Q differential output voltages that can be connected directly to an RF modulator at the TXOP and TXON pins.The DSP is notified when the transmission is completed. For receiving baseband data, a DSP can program CSP1093sevent timing and control register with the exact time to start receiving I and Q samples through TXIP and TXIN pins.When that time is reached, the control portion of the event timing and control register will start the baseband receivesection converting I and Q sample pairs. The samples are stored in a double-buffered register until the register contains32 sample pairs. CSP1093 then notifies the DSP which has ample time to read the information out before the next 32sample pairs are stored. The voice band ADC converter issues an interrupt to the DSP whenever it finishes converting a16-bit PCM word. The DSP then reads the new input sample and simultaneously loads the voice band output DACconverter with a new PCM output word. The voice band output can be connected directly to a speaker via AOUTAN andAOUTAP pins and be connected to a Ear-mic speaker via AOUTBN and AOUTBP pins.8. X-TAL(13MHz)This system uses the 13MHz TCXO, TCO-9141B, Toyocom. AFC control signal form CSP1093 controls frequency from13MHz x-tal. It generates the clock frequency. This clock is inverted through NOT gate, TC7S04FU and is connected toCSP1093. 13MHz clock for YMU759 uses a not-inverted clock. Clock for RF parts uses same type.SAMSUNG Proprietary-Contents may change without notice


9.Camera DSP(LC99704B)- This chipset is MCP product that combines the CCD Driver with on-chip booster circuitand analogue/digital mixed-signal processing IC.The booster circuit generate the supply voltages required for CCD drive.Cameras can use either a +2.8V or +3.0V or +3.3V only power supply system.The analogue / digital mixed-signal processing IC that integrates the signal-processingfunctions required in a CCD digital camera and a rich set of addtional functions on a singlechip. Although the CDS(correlated dual sampling) and AGC circuit required for analogprocessing and the clamp circuit required for A/D conversion are normally povided oncircuits, as well as an A/D converter, on a single chip.Additionally, it also includes the pulse generator circuits required for CCD drive, thelogic circuits for the electronics iris, and the digital signal-processing circuits required tocreate the digital YUV signal output. This device can take advantage of the features ofthese digital signal-processing functions to provide auto white balance, automatic dropoutdetection and correction, mirror image output, and a single line of memory to provideflexibility in the external interface.This device assumes an internal master clock frequency in the range 16 ~27 MHz.Normally , either an external clock with that frequency is provided, or else a master clockoscillator circuit is constructed using the built-in oscillator inverter circuit.And this is also possible to control the CCD drive internal and enternal.10. Camera ASIC(SSH 275)This ASIC interfaces between CCD and LCD, and this chip compresses and expandsinput pictures from CCD with JPEG format.- CCD I/F : YUV422(16 bit) format, CIF fixed size.System clock providing CCD module (13.5 MHz) and Dot clock providingCCD module (13.5 MHz).- CPU I/F : Accessible to JPEG controller, a control register including, JPEG code buffer,and a thumbnail picture buffer.Direct access to LCD controller by switching buses.- LCD I/F : Support LCD controller.Accessible by switching 2 masters of the Host CPU or ASIC pictureprocessing .Output format from ASIC is RGB565.- I2C I/F : I2C master for CCD module control equipped.CCD module is accessible from CPU wiithout paying attention to I2C, as in thecase of a normal register write/read.- JPEG codec : YUV422 picture data is compressed to JPEG code, and JPEG code data isexpanded to YUV422 picture data.- Clock system : As for ASIC, 27 MHz clock input from outside is the main clock.2-divided 13.5 MHz is used as CCD module main clock output, dot clockoutput to CCD module, and ASIC inner clockSAMSUNG Proprietary-Contents may change without notice


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9. EGSM transmitter SAMSUNG Proprietary-Contents may change without notice


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12. DPCS transmitter SAMSUNG Proprietary-Contents may change without notice


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ELECTRONICS

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