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drivers: spi: spi_mcux_lpspi: inconsistent chip select behaviour #16544
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@MaureenHelm is this issue being looked at? |
Not yet, but going to try to look at it tomorrow. |
This is caused by the underlying MCUX SDK LPSPI driver missing a feature to hold the chip select active after a transfer. The underlying MCUX SDK DSPI driver used on frdm_k64f has a Decreasing the priority of this bug from medium to low since we can work around it with GPIO CS. |
This is still an issue with the most recent MCUX SDK (I was just bitten by this issue on bringing up a newly developed board today). Should we change all affected in-tree boards to use |
@henrikbrixandersen i've encountered similar issues with SPI on LPC55xxx, see my 2 pulls:
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Re-opening after discord discussion, as this issue is still relevant. |
If (If |
This issue has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this issue will automatically be closed in 14 days. Note, that you can always re-open a closed issue at any time. |
This issue has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this issue will automatically be closed in 14 days. Note, that you can always re-open a closed issue at any time. |
This issue has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this issue will automatically be closed in 14 days. Note, that you can always re-open a closed issue at any time. |
I produced this code to try to reproduce the issue on mimxrt1024_evk on commit b573f44 based on what was originally posted by @henrikbrixandersen :
With DT overlay
And I observed the behavior to be the same whether or not the cs-gpios property was commented out of the DT or not. The behavior of both versions being that the CS is deasserted between the parts of the transfer. Please someone who had this issue please confirm if I missed something in this code or if the behavior did indeed change in the last 5 years, or maybe the issue is specific to only some platforms |
I can try to reproduce this when I return from Seattle. My original finding was on the |
Describe the bug
The MCUX LPSPI SPI driver handles SPI chip selects inconsistently when comparing GPIO CS and "native" controller CS handling over multipart transfers.
With GPIO CS enabled (where the LPSPI controller does not control the CS line), the CS line is kept asserted through the entire transfer. This is opposed to what happens when the CS line is controlled by the LPSPI controller itself; then the CS line is deasserted between the different parts of the transfer.
To Reproduce
Expected behavior
The CS line remains asserted through all the parts of the multipart transfer.
Impact
Deasserting the CS line in the middle of a transfer causes problem e.g. when communicating with SPI EEPROMs.
Screenshots or console output
When using GPIO CS:
When using LPSPI CS:
Environment (please complete the following information):
Additional context
This was spotted when trying to use a SPI EEPROM with the TWR-KE18F board, but it is not limited to that board nor to the KE1xF SoC series, as far as I can tell.
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